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0.8 ghz to 2.5 ghz quadrature modulator ad8346 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features high accuracy 1 degree rms quadrature error @ 1.9 ghz 0.2 db i/q amplitude balance @ 1.9 ghz broad frequency range: 0.8 ghz to 2.5 ghz sideband suppression: ?46 dbc @ 0.8 ghz sideband suppression: ?36 dbc @ 1.9 ghz modulation bandwidth: dc to 70 mhz 0 dbm output compression level @ 0.8 ghz noise floor: ?147 dbm/hz single 2.7 v to 5.5 v supply quiescent operating current: 45 ma standby current: 1 a 16-lead tssop applications digital and spread spectrum communication systems cellular/pcs/ism transceivers wireless lan/wireless local loop qpsk/gmsk/qam modulators single-sideband (ssb) modulators frequency synthesizers image reject mixer functional block diagram 1 2 3 4 5 6 7 8 bias phase splitter 16 15 14 13 12 11 10 9 ad8346 ibbp ibbn com1 com1 loin loip vps1 enbl qbbp qbbn com4 com4 vps2 vout com3 com2 05335-001 figure 1. general description the ad8346 is a silicon rfic i/q modulator for use from 0.8 ghz to 2.5 ghz. its excellent phase accuracy and amplitude balance allow high performance direct modulation to rf. the differential lo input is applied to a polyphase network phase splitter that provides accurate phase quadrature from 0.8 ghz to 2.5 ghz. buffer amplifiers are inserted between two sections of the phase splitter to improve the signal-to- noise ratio. the i and q outputs of the phase splitter drive the lo inputs of two gilbert-cell mixers. two differential v-to-i converters connected to the baseband inputs provide the baseband modulation signals for the mixers. the outputs of the two mixers are summed together at an amplifier which is designed to drive a 50 load. this quadrature modulator can be used as the transmit mod- ulator in digital systems such as pcs, dcs, gsm, cdma, and ism transceivers. the baseband quadrature inputs are directly modulated by the lo signal to produce various qpsk and qam formats at the rf output. additionally, this quadrature modulator can be used with direct digital synthesizers in hybrid phase-locked loops to generate signals over a wide frequency range with millihertz resolution. the ad8346 comes in a 16-lead tssop package, measuring 6.5 mm 5.1 mm 1.1 mm. it is specified to operate over a ?40c to +85c temperature range and a 2.7 v to 5.5 v supply voltage range. the device is fabricated on analog devices high performance 25 ghz bipolar silicon process.
ad8346 rev. a | page 2 of 20 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 equivalent circuits ........................................................................... 6 typical performance characteristics ............................................. 7 circuit description ......................................................................... 10 overview ...................................................................................... 10 lo interface ................................................................................. 10 v-to-i converter ......................................................................... 10 mixers .......................................................................................... 10 differential-to-single-ended converter ................................. 10 bias ............................................................................................... 10 basic connections ...................................................................... 11 lo drive ...................................................................................... 11 rf output .................................................................................... 11 interface to ad9761 t x dac? .................................................. 12 ac-coupled interface ............................................................... 13 evaluation board ............................................................................ 14 characterization setups ................................................................. 16 ssb setup ..................................................................................... 16 cdma setup ............................................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 6/05rev. 0 to rev. a updated format..................................................................universal changes to figures 30, 31, 32........................................................ 14 update outline dimensions ......................................................... 18 changes to ordering guide .......................................................... 18 3/99revision 0: initial version
ad8346 rev. a | page 3 of 20 specifications v s = 5 v; t a = 25c; lo frequency = 1900 mhz; lo level = C10 dbm; bb frequency = 100 khz; bb inputs are dc-biased to 1.2 v; bb input level = 1.0 v p-p each pin for 2.0 v p-p differential drive; lo source and rf output load impedances are 50 , dbm units are re ferenced to 50 unless otherwise noted. table 1. parameters conditions min typ max unit rf output operating frequency 0.8 2.5 ghz quadrature phase error see figure 35 for setup 1 degree rms i/q amplitude balance see figure 35 for setup 0.2 db output power i and q channels in quadrature ?13 ?10 ?6 dbm output vswr 1.25:1 output p1 db ?3 dbm carrier feedthrough ?42 ?35 dbm sideband suppression ?36 ?25 dbc im3 suppression ?60 dbc equivalent output ip3 20 dbm output noise floor 20 mhz offset from lo ?147 dbm/hz response to cdma is95 baseband signals acpr (adjacent channel power ratio) see figure 35 for setup ?72 dbc evm (error vector magnitude) see figure 35 for setup 2.5 % rho (waveform quality factor) see figure 35 for setup 0.9974 modulation input input resistance 12 k modulation bandwidth ?3 db 70 mhz lo input lo drive level ?12 ?6 dbm input vswr 1.9:1 enable enbl hi threshold 2.0 v enbl lo threshold 0.5 v enbl turn-on time settle to within 0.5 db of final ssb output power 2.5 s enbl turn-off time time for supply current to drop below 2 ma 12 s power supplies voltage 2.7 5.5 v current active (enbl hi) 35 45 55 ma current standby (enbl lo) 1 20 a
ad8346 rev. a | page 4 of 20 absolute maximum ratings table 2. parameter min rating supply voltage vps1, vps2 5.5 v input power loip, loin (r elative to 50 ) 10 dbm min input voltage ibbp, ibbn, qbbp, qbbn 0 v max input voltage ibbp, ibbn, qbbp, qbbn 2.5 v internal power dissipation 500 mw ja 125c/w operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8346 rev. a | page 5 of 20 pin configuration and fu nction descriptions 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ibbp qbbp ad8346 top view (not to scale) ibbn qbbn com1 com4 com1 com4 loin vps2 loip vout vps1 com3 enbl com2 05335-002 figure 2. pin configuration table 3. pin function descriptions pin o. neonic description uivalent ircuit 1 ibbp i channel baseband positive input pin. input sh ould be dc-biased to approximately 1.2 v. nominal characterized ac swing is 1 v p-p (0.7 v to 1.7 v). this makes the differential input 2 v p-p when ibbn is 180 degrees out of phase from ibbp. circuit a 2 ibbn i channel baseband negative input pin. input should be dc-bia sed to approximately 1.2 v. nominal characterized ac swing is 1 v p-p (0.7 v to 1.7 v). this makes the differential input 2 v p-p when ibbn is 180 degrees out of phase from ibbp. circuit a 3 com1 ground pin for the lo phase splitter and lo buffers. 4 com1 ground pin for the lo phase splitter and lo buffers. 5 loin lo negative input pin. internal dc bias (approximately vps1 to 800 mv) is supplied. this pin must be ac coupled. circuit b 6 loip lo positive input pin. internal dc bias (approx imately vps1 to 800 mv) is supplied. this pin must be ac-coupled. circuit b 7 vps1 power supply pin for the bias cell and lo bu ffers. this pin should be decoupled using local 100 pf and 0.01 f capacitors. 8 enbl enable pin. a high level enables the device; a low level puts the device in sleep mode. circuit c 9 com2 ground pin for the input stage of output amplifier. 10 com3 ground pin for the output stage of output amplifier. 11 vout 50 dc-coupled rf output. user must provide ac coupling on this pin. circuit d 12 vps2 power supply pin for baseband input voltage to current converters and mixer core. this pin should be decoupled using lo cal 100 pf and 0.01 f capacitors. 13 com4 ground pin for baseband input volt age to current converters and mixer core. 14 com4 ground pin for baseband input volt age to current converters and mixer core. 15 qbbn q channel baseband negative input. input should be dc biased to approximately 1.2 v. nominal characterized ac swing is 1 v p-p. th is makes the differential input 2 v p-p when qbbn is 180 out of phase from qbbp. circuit a 16 qbbp q channel baseband positive input. input shou ld be dc-biased to approximately 1.2 v. nominal characterized ac swing is 1 v p-p. th is makes the differential input 2 v p-p when qbbn is 180 out of phase from qbbp. circuit a
ad8346 rev. a | page 6 of 20 equivalent circuits 3k 9k vps2 input buffer to mixer core active loads 05335-003 figure 3. circuit a vps1 loin loip phase splitter continues 05335-004 figure 4. circuit b 40k 30k vps1 to bias for startup/ shutdown 780 75k enbl 75k 05335-005 figure 5. circuit c 43 43 vps2 v out 05335-006 figure 6. circuit d
ad8346 rev. a | page 7 of 20 typical performance characteristics lo frequency (mhz) ssb power (dbm) ?6 ?7 ?8 ?9 ?10 ?11 ?12 ?13 ?14 ?15 1200 1600 2000 2400 800 1400 1800 2200 1000 t = 25c v p = 5.5v v p = 5v v p = 2.7v v p = 3v 05335-007 figure 7. single sideband (ssb) output power (p out ) vs. lo frequency (f lo ). i and q inputs driven in quadrature at baseband frequency (f bb ) = 100 khz with differential amplitude of 2.00 v p-p. ssb output power (dbm) ?6 ?7 ?8 ?9 ?10 ?11 ?12 ?13 lo = 1900mhz, ?10dbm lo = 800mhz, ?10dbm lo = 1900mhz, ?6dbm lo = 800mhz, ?6dbm temperature (c) ?40 ?20 0 20304050607080 ?30 ?10 10 05335-008 figure 8. ssb p out vs. temperature. i and q inputs driven in quadrature with differential amplitude of 2.00 v p-p at f bb = 100 khz. temperature (c) carrier feedthrough (dbm) ?35 ?40 ?20 0 20304050607080 ?37 ?39 ?41 ?43 ?45 ?47 ?49 ?51 ?30 ?10 10 v p = 5v v p = 5.5v v p = 3v v p = 2.7v 05335-009 figure 9. carrier feedthrough vs. temperature. f lo = 1900 mhz, lo input level = C10 dbm. baseband frequency (mhz) output power variation (db) 2 0.1 1 100 10 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 05335-010 figure 10. i and q input bandwidth. f lo =1900 mhz, i or q inputs driven with differential amplitude of 2.00 v p-p. lo frequency (mhz) ssb output p1db (dbm) 2 800 0 ?2 ?4 ?6 ?8 ?10 ?12 1000 ?14 1200 1400 1600 1800 2000 2200 2400 v p = 2.7v t = ?40c v p = 2.7v t = +85c v p = 5v t = ?40c v p = 5v t = +85c 05335-011 figure 11. ssb output 1 db compression point (op 1 db) vs. flo. i and q inputs driven in quadrature at f bb = 100 khz. carrier feedthrough (dbm/ after nulling to ad8346 rev. a | page 8 of 20 ssb output power (dbm) ?7 ?8 ?9 ?10 ?11 ?12 ?13 ?14 ?15 v p = 5v v p = 3v v p = 5.5v v p = 2.7v temperature (c) ?40 ?20 0 20304050607080 ?30 ?10 10 05335-013 figure 13. ssb p out vs. temperature. f lo = 1900 mhz, i and q inputs driven in quadrature with differential amplitude of 2.00 v p-p at f bb = 100 khz. lo frequency (mhz) carrier feedthrough (dbm) ?36 ?38 ?40 ?42 ?44 ?46 ?48 ?50 ?52 ?54 1200 1600 2000 2400 800 1400 1800 2200 1000 t = 25c v p = 3v v p = 5.5v v p = 5v v p = 2.7v 05335-014 figure 14. carrier feedthrough vs. f lo . lo input level = C10 dbm. lo frequency (mhz) sideband suppression (dbc) ?32 ?34 ?36 ?38 ?40 ?42 ?44 ?46 ?48 1300 1700 2100 2500 900 1500 1900 2300 1100 t = 25c v p = 3v v p = 2.7v v p = 5v v p = 5.5v 05335-015 figure 15. sideband suppression vs. f lo . v pos = 2.7 v, i and q inputs driven in quadrature with differential amplitude of 2.00 v p-p at f bb = 100 khz. baseband frequency (mhz) sb suppression (dbc) ?30 0 ?32 ?34 ?36 ?38 ?40 ?42 ?44 2 4 6 8 10 12 14 16 18 20 05335-016 v p = 3v v p = 5.5v v p = 2.7v v p = 5v figure 16. sideband suppression vs. f bb . f lo = 1900 mhz, i and q inputs driven in quadrature with differential amplitude of 2.00 v p-p. input third harmonic distortion (dbc) ?35 ?40 ?45 ?50 ?55 ?60 ?65 ?70 05335-017 temperature (c) ?40 ?20 0 20304050607080 ?30 ?10 10 v p = 5.5v v p = 2.7v v p = 3v v p = 5v figure 17. third harmonic distortion vs. temperature. f lo =1900 mhz, i and q inputs driven in quadrature with differential amplitude of 2.00 v p-p at f bb = 100 khz. frequency (mhz) 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 800 1200 1600 2000 ?20 return loss (db) 2400 ?16 ?18 1400 1800 2200 1000 05335-018 t = +25 c t = +85c t = ?40c figure 18. return loss of loin input vs. f lo . v pos = 5.0 v, loip pin ac-coupled to ground.
ad8346 rev. a | page 9 of 20 sb suppression (dbc) ?30 ?32 ?34 ?36 ?38 ?40 ?42 ?44 05335-019 temperature (c) ?40 ?20 0 20304050607080 ?30 ?10 10 v p = 5v v p = 2.7v v p = 3v v p = 5.5v figure 19. sideband suppression vs. temperature. f lo = 1900 mhz, i and q inputs driven in quadrature with differential amplitude of 2.00 v p-p at f bb = 100 khz. baseband differential input voltage (v p-p) input third harmonic distortion (dbc) ?30 0.5 ?35 ?40 ?45 ?50 ?55 1.0 1.5 2.0 2.5 3.0 ?60 ?65 ?70 ?75 ?80 ?6 ?8 ?10 ?12 ?14 ?16 ?18 ?20 ?22 ssb output power (dbm) 05335-020 ssb p out 3rd harmonic figure 20. third harmonic distortion and ssb output power vs. baseband differential input voltage level. f lo = 1900 mhz, i and q inputs driven in quadrature at f bb = 100 khz. frequency (mhz) 0 ?5 ?10 ?15 ?20 ?25 ?30 800 1200 1600 2000 ?40 return loss (db) 2400 ?35 1400 1800 2200 1000 05335-021 t = ?40c t = +25c t = +85c figure 21. return loss of v out output vs. f lo . v pos = 2.7 v. baseband frequency (mhz) input third harmonic distortion (db)c ?40 0 ?45 ?50 ?55 ?60 ?65 2468101214161820 05335-022 v p = 5v v p = 5.5v v p = 2.7v v p = 3v figure 22. third harmonic distortion vs. f bb . f lo =1900 mhz, i and q inputs driven in quadrature with differential amplitude of 2.00 v p-p. 52 50 48 46 44 42 40 38 36 supply current (ma) 05335-023 temperature (c) ?40 ?20 0 20 40 60 80 v p = 5v v p = 2.7v v p = 3v v p = 5.5v figure 23. power supply current vs. temperature frequency (mhz) 0 ?5 ?10 ?15 ?20 ?25 ?30 800 1200 1600 2000 ?40 return loss (db) 2400 ?35 1400 1800 2200 1000 05335-024 t = ?40c t = +25c t = +85c figure 24. return loss of v out output vs. f lo . v pos = 5.0 v.
ad8346 rev. a | page 10 of 20 circuit description overview the ad8346 can be divided into the following sections: local oscillator (lo) interface, mixer, voltage-to-current (v-to-i) converter, differential-to-single-ended (d-to-s) converter, and bias. a detailed block diagram of the part is shown in figure 25 . the lo interface generates two lo signals, with 90 of phase difference between them, to drive two mixers in quadrature. baseband voltage signals are converted into current form in the v-to-i converters, feeding into two mixers. the output of the mixers are combined to feed the d-to-s converter which provides the 50 output interface. bias currents to each section are controlled by the enable (enbl) signal. detailed descriptions of each section follows. lo interface the differential lo inputs allow the user to drive the lo differ- entially in order to achieve maximum performance. the lo can be driven single-endedly but the lo feedthrough performance is degraded, especially towards the higher end of the frequency range. the lo interface consists of interleaved stages of polyphase network phase splitters and buffer amplifiers. the phase-splitter contains resistors and capacitors connected in a circular manner to split the lo signal into i and q paths in precise quadrature with each other. the signal on each path goes through a buffer amplifier to make up for the loss and high frequency roll-off. the two signals then go through another polyphase network to enhance the quadrature accuracy. the broad operating frequency range of 0.8 ghz to 2.5 ghz is achieved by staggering the rc time constants in each stage of the phase-splitters. the outputs of the second phase-splitter are fed into the driver amplifiers for the mixers lo inputs. v-to-i converter each baseband input pin is connected to an op amp driving an emitter follower. feedback at the emitter maintains a current proportional to the input voltage through the transistor. this current is fed to the two mixers in differential form. mixers there are two double-balanced mixers, one for the in-phase channel (i-channel) and one for the quadrature channel (q channel). each mixer uses the gilbert cell design with four cross-connected transistors. the bases of the transistors are driven by the lo signal of the corresponding channel. the output currents from the two mixers are summed together in two resistors in series with two coupled on-chip inductors. the signal developed across the r-l loads is sent to the d-to-s stage. differential-to-sing le-ended converter the differential-to-single-ended converter consists of two emitter followers driving a totem-pole output stage. output impedance is established by the emitter resistors in the output transistors. the output of this stage is connected to the output (vout) pin. bias a band gap reference circuit based on the -v be principle generates the proportional-to-absolute-temperature (ptat) currents used by the different sections as references. the band gap voltage is also used to generate a temperature-stable current in the v-to-i converters to produce a temperature-independent slew rate. when the band gap reference is disabled by pulling down the enbl pin, all other sections are shut off accordingly. mixer mixer v-to-i v-to-i v-to-i v-to-i d-to-s bias cell ad8346 loin loip enbl qbbp qbbn v ou t ibbn ibbp phase splitter 1 phase splitter 2 05335-025 figure 25. detailed block diagram
ad8346 rev. a | page 11 of 20 basic connections the basic connections for operating the ad8346 are shown in figure 27 . a single power supply of between 2.7 v and 5.5 v is applied to pins vps1 and vps2. a pair of esd protection diodes are connected internally between vps1 and vps2 so these must be tied to the same potential. both pins should be individually decoupled using 100 pf and 0.01 f capacitors, located as close as possible to the device. for normal operation, the enable pin, enbl, must be pulled high. the turn-on threshold for enbl is 2 v. to put the device in its power-down mode, enbl must be pulled below 0.5 v. pins com1 to com4 should all be tied to a low impedance ground plane. the i and q ports should be driven differentially. this is con- venient as most modern high speed dacs have differential outputs. for optimal performance, the drive signal should be a 2 v p-p (differential) signal with a bias level of 1.2 v, that is, each input swings from 0.7 v to 1.7 v. the i and q inputs have input impedances of 12 k. by dc coupling the dac to the ad8346 and applying small offset voltages, the lo feedthrough can be reduced to well below its nominal value of ?42 dbm (see figure 12 ). lo drive the return loss of the lo port is shown in figure 18 . no add- itional matching circuitry is required to drive this port from a 50 source. for maximum lo suppression at the output, a differential lo drive is recommended. in figure 27 , this is achieved using a balun (m/a-com part number etc1-1-13). the output of the balun is ac-coupled to the lo inputs which have a bias level about 800 mv below supply. an lo drive level of between ?6 dbm and ?12 dbm is required. for optimal performance, a drive level of ?10 dbm is recommended, although a level of ?6 dbm results in more stable temperature performance (see figure 8 ). higher levels degrade linearity while lower levels tend to increase the noise floor. loip loin ad8346 100pf 100pf lo 05335-026 figure 26. single-ended lo drive the lo terminal can be driven single-ended, as shown in figure 26 at the expense of slightly higher lo feedthrough. loin is ac coupled to ground using a capacitor and loip is driven through a coupling capacitor from a (single-ended) 50 source (this scheme could also be reversed with loip being ac-coupled to ground). rf output the rf output is designed to drive a 50 load, but must be ac- coupled, as shown in figure 27 . if the i and q inputs are driven in quadrature by 2 v p-p signals, the resulting output power is about ?10 dbm (see figure 7 for variations in output power over frequency). qbbp ibbp ad8346 qbbn ibbn com4 com1 com4 com1 vps2 loin vout loip com3 vps1 com2 enbl 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c4 0.01 f c3 100pf c6 100pf c7 100pf t1 etc1-1-13 1 2 3 5 4 c2 0.01 f c1 100pf c5 100pf ip in lo +v s qp qn +v s vout 05335-027 figure 27. basic connections
ad8346 rev. a | page 12 of 20 interface to ad9761 t x dac? figure 28 shows a dc-coupled current output dac interface. the use of dual-integrated dacs, such as the ad9761 with specified 0.02 db and 0.004 db gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. the use of a precision thin-film resistor network sets the bias levels precisely to prevent the introduction of offset errors, which increase lo feedthrough. for instance, selecting resistor networks with a 0.1% ratio matching characteristics maintains 0.03 db gain and offset matching performance. using resistive division, the dc bias level at the i and q inputs to the ad8346 is set to approximately 1.2 v. each of the four current outputs of the dac delivers a full-scale current of 10 ma, giving a voltage swing of 0 v to 1 v (at the dac output). this results in a 0.5 v p-p swing at the i and q inputs of the ad8346 (resulting in a 1 v p-p differential swing). note that the ratio matching characteristics of the resistive network, as opposed to its absolute accuracy, is critical in preserving the gain and offset balance between the i and q signal path. by applying small dc offsets to the i and q signals from the dac, the lo suppression can be reduced from its nominal value of ?42 dbm to as low as ?60 dbm while holding to approximately ?50 dbm over temperature (see figure 12 for a plot of lo feedthrough over temperature for an offset compensated circuit). i dac 2 latch i ioutb iouta q dac 2 latch q qoutb qouta mux control select write clock ad9761 dvdd dcom avdd 0.1 f r set 2k sleep fs adj refio dac data inputs c filter 100 100 c filter 100 100 500 500 500 500 500 500 500 500 0.1 f 634 5v phase splitter vout ibbp ibbn qbbp qbbn ad8346 loip loin vps1 vps2 0.5v p-p each pin with v cm = 1.2v +5v 05335-028 figure 28. ad8346 interface to ad9761 txdac
ad8346 rev. a | page 13 of 20 ac-coupled interface an ac-coupled interface can also be implemented, as shown in figure 29 . this is an advantage because there is almost no voltage loss due to the biasing network, allowing the ad8346 inputs to be driven by the full 2 v p-p differential signal from the ad9761 (each of the dacs 4 outputs delivering 1 v p-p). as in the dc-coupled case, the bias levels on the i and q inputs should be set to as precise a level as possible, relative to each other. this prevents the introduction of additional input offset voltages. in figure 29 , the bias level on each input is set to approximately 1.2 v. the 2.43 k resistors should have a ratio tolerance of 0.1% or better. the network shown has a high-pass corner frequency of approximately 14.3 khz (note that the 12 k input impedance of the ad8346 has been factored into this calculation). increasing the resistors in the network or increasing the coupling capacitance reduces the corner frequency further. note that the lo suppression can be manually optimized by replacing a portion of the four top 2.43 k resistors with potentiometers. in this case, the bottom four resistors in the biasing network no longer need to be precision devices. 2 latch i ioutb iouta 2 latch q qoutb qouta mux control select write clock ad9761 dvdd dcom avdd 0.1 f r set 2k sleep fs adj refio dac data inputs c filter 100 100 c filter 100 100 0.1 f 1k 5v phase splitter vout ibbp ibbn qbbp qbbn ad8346 loip loin vps1 vps2 1v p-p each pin with v cm = 1.2v 5v 0.01 f 0.01 f 0.01 f 0.01 f i dac 2.43k 2.43k 2.43k 2.43k 2.43k 2.43k 2.43k 2.43k q dac 05335-029 figure 29. ac-coupled dac interface
ad8346 rev. a | page 14 of 20 evaluation board the schematic of the ad8346 evaluation board is shown in figure 30 . this is a 4-layer fr4 board; the two center layers are used as ground planes and the top and bottom layers are used for signal and power. figure 31 shows the layout and figure 32 shows the silkscreen. the evaluation board circuit closely follows the basic connections circuit shown in figure 27 . slide sw1 to the a position to connect the enbl pin to +v s via the 10 k pull-up resistor rep. slide sw1 to the b position to disable the device by grounding the enop pin through the 49.9 pull-down resistor reg. the device may be enabled via an external voltage applied to the sma connector enop or tp2. all connectors are of the sma type. the i and q inputs are provided with pads for implementing a simple rc filter network. the local oscillator input is driven through a balun (m/a-com part number etc1-1-13). 05335-030 c4 100pf c3 0.01 f qp qn clop 100pf clon 100pf lo rlop open rlon open rlos open 1 2 3 4 5 6 7 8 16 15 14 13 12 10 9 11 ibbp ibbn com1 com1 loin loip vps1 enbl qbbp qbbn com4 com4 vps2 vout com3 com2 tp2 enop ip in enop cvo 100pf vout +v s +v s ad8346 rqp 0 cqp open rqn 0 r2 0 cip open rip 0 rin 0 cin open c1 0.01 f c2 100pf r7 0 t1 etc1-1-13 1 2 3 5 4 ris open rqs open cqn open reg 49.9k rep 10k a b sw1 figure 30. evaluation board schematic
ad8346 rev. a | page 15 of 20 05335-031 figure 31. layout of evaluation board 05335-032 figure 32. silkscreen of evaluation board
ad8346 rev. a | page 16 of 20 characterization setups ssb setup two main setups were used to characterize this product. these setups are shown in figure 33 and figure 35 . figure 33 shows the setup used to evaluate the product as an ssb. the ad8346 motherboard had circuitry that converted the single-ended i and q inputs from the arbitrary function generator to differ- ential inputs with a dc bias of approximately 1.2 v. in addition, the motherboard also provided connections for power supply routing. the hp34970a and its associated plug-in 34901 were used to monitor power supply currents and voltages being supplied to the ad8346 evaluation board (a full schematic of the ad8346 evaluation board can be found in figure 30 ). the two hp34907 plug-ins were used to provide additional miscellaneous dc and control signals to the motherboard. the lo was driven by an rf signal generator (through the balun on the evaluation board to present a differential lo signal to the device) and the output was measured with a spectrum analyzer. with the i channel driven with a sine wave and the q channel driven with a cosine wave, the lower sideband is the single sideband output. the typical ssb output spectrum is shown in figure 34 . vps1 vn gnd vp ad8346 motherboard i in q in d1 d2 d3 p1 in ip qp qn ieee 34901 34907 34907 d1 d2 d3 hp34970a ad8346 eval board p1 in ip qp qn lo enbl vout rfout ieee hp8648c +15v max com +25v max ?25v max ieee hp3631 ieee pc controller hp8593e rf i/p cal out 28volt ieee spectrum analyzer sweep out output 1 output 2 ieee tekafg2020 arb func. gen 05335-033 figure 33. evaluation board ssb test setup 0 center 1.9ghz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 50khz/ span 500khz 05335-034 figure 34. typical ssb output spectrum
ad8346 rev. a | page 17 of 20 cdma setup for evaluating the ad8346 with cdma waveforms, the setup shown in figure 35 was used. this is essentially the same setup as that used for the single sideband characterization, except that the afg2020 was replaced with the awg2021 for providing the i and q input signals, and the spectrum analyzer used to monitor the output was changed to an fsea30 rohde & schwarz analyzer with vector demodulation capability. the i/q input signals for these measurements were is95 baseband signals generated with tektronix i/q sim software and downloaded to the awg2021. for measuring acpr, the i/q input signals used were generated with pilot (walsh code 00), sync (wc 32), paging (wc 01), and 6 traffic (wc 08, 09, 10, 11, 12, 13) channels active. the i/q sim software was set for 32 oversampling and was using a bs equifilter. figure 36 shows the typical output spectrum for this configuration. the acpr was measured 885 khz away from the carrier frequency. for performing evm, rho, phase, and amplitude balance measurements, the i/q input signals used were generated with only the pilot channel (walsh code 00) active. the i/q sim software was set for 32 oversampling using a cdma equifilter. vps1 vn gnd vp ad8346 motherboard i in q in d1 d2 d3 p1 in ip qp qn ieee 34901 34907 34907 d1 d2 d3 hp34970a ad8346 eval board p1 in ip qp qn lo enbl vout rfout ieee hp8648c +15v max com +25v max ?25v max ieee hp3631 ieee pc controller fsea30 rf i/p ieee spectrum analyzer output 1 output 2 ieee tekafg2020 arb func. gen 05335-035 figure 35. evaluation board cdma test setup ?20 center 1.9ghz ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 ? 110 ? 120 187.5khz/ span 1.875mhz ch pwr = ?20.7dbm acp upr = ?71.8dbc acp lwr = ?71.7dbc 05335-036 figure 36. typical cdma output spectrum
ad8346 rev. a | page 18 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab figure 37.16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range package description package option ad8346aru ?40c to +85c 16-lead thin shri nk small outline package (tssop) ru-16 ad8346aru-reel ?40c to +85c 16-lead (tssop) 13" tape and reel ru-16 ad8346aru-reel7 ?40c to +85c 16-lead (tssop) 7" tape and reel ru-16 AD8346ARUZ-reel 1 ?40c to +85c 16-lead (tssop) 13" tape and reel ru-16 AD8346ARUZ-reel7 1 ?40c to +85c 16-lead (tssop) 7" tape and reel ru-16 ad8346-eval evaluation board 1 z = pb-free part.
ad8346 rev. a | page 19 of 20 notes
ad8346 rev. a | page 20 of 20 notes ?2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the proper ty of their respective companies. c05335C0C6/05(a)

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